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Chinese Chipmakers Pay a Heavy Price for EUV Workarounds

China's chipmakers are finding ways to bypass export controls on advanced lithography tools, but the methods they use to do so come with significant financial and manufacturing costs.

By Jonathan Hoffmann ·

Illustration for: Chinese Chipmakers Pay a Heavy Price for EUV Workarounds
Illustration generated for this article, not a news photograph.

China's semiconductor industry has found a way to produce advanced chips despite export restrictions on the most powerful manufacturing tools, but this workaround comes with a significant price tag. Chinese chipmakers are using a technique that increases production time, the potential for defects, and overall costs, according to experts. The approach involves multiple patterning, a method that uses older technology to achieve results similar to that of more advanced equipment.

Export controls have prevented China from acquiring ASML's extreme ultraviolet (EUV) lithography machines, which are essential for manufacturing the smallest and most complex chips. Without these tools, Chinese firms rely on older deep ultraviolet (DUV) equipment. To create the intricate layers of a modern processor, manufacturers using DUV must expose a wafer to light multiple times, building up the design step by step. This process, known as multiple patterning, enables the production of capable silicon, but each additional exposure introduces new challenges.

The process of exposing a wafer multiple times increases the risk of defects and lengthens production times. Each new pattern must align perfectly with the previous one, and small errors can accumulate with each step. To compensate for these errors, designers may need to add extra space around the features on a chip, which makes the chip larger and reduces the number of chips that can be produced from a single wafer. This is a costly outcome, as wafers can cost tens of thousands of dollars each. 'You don't sell wafers, you sell die,' said Chris Mack, co-founder and CTO of semiconductor firm Fractilia.

The efficiency gap is particularly evident in memory chip production. A June report from Morgan Stanley estimated that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as its Western competitors, identifying lithography access as a 'hard ceiling' for Chinese memory development. Mack also noted that labels like 5nm or 3nm are not directly comparable, as SMIC's N+3 process is less advanced than the 5nm processes from Samsung and TSMC.

Despite these hurdles, Chinese chipmakers are not at a standstill. They can continue to use DUV technology while accepting larger dies, lower yields, and longer production times. They can also expand their manufacturing capacity to increase output. Morgan Stanley assumes CXMT will continue using DUV for its 1-alpha DRAM, yet still expects the company to increase its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new capacity.

The bank also projects that China's AI chip self-sufficiency will rise from 42% in 2025 to 70% by 2030. However, a persistent gap will remain in areas such as EUV, HBM, and advanced software. While Chinese firms can produce capable chips without EUV, the trade-offs involved are significant and costly, and experts do not expect the most advanced nodes to be economically viable without it.

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